1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a stack chip module improving heat release properties and electric and mechanical reliability.
2. Description of the Related Art
As high-performance electric appliances are developed, efforts are focused on research to mount a large number of packages on a limited substrate. However, generally, one semiconductor chip is loaded in a package, making it difficult to obtain desired capacitance.
A method has been proposed in which a large number of cells are fabricated in a limited area in order to increase capacitance of a memory chip, that is, to accomplish high integration. However, the method requires difficult processes for fine line width and much development time. Therefore, a stacking method has been developed in order to accomplish high integration with ease.
The stacking method increases memory capacitance by stacking two or more semiconductor chips. According to the stacking method, two 64 M DRAM level chips are stacked to obtain a 128 M DRAM level and two 128 M DRAM level chips are stacked to obtain a 256 M DRAM level.
In order to stack two semiconductor chips, two packaged packages are stacked. Alternatively, two stacked bare chips are arranged in a package. FIGS. 1 and 2 show stack packages according to conventional methods.
FIG. 1 is a cross sectional view showing a conventional stack package according to a first method. As shown in FIG. 1, two semiconductor packages 10a, 10b are arranged in a stacked arrangement wherein an outer lead of the top package 10a is bonded to that of the bottom package 10b. In the packages 10a, 10b, lead frames 4a, 4b are adhered on one side of each semiconductor chip 1a, 1b by adhesives 3a, 3b, all respectively. Inner leads of each lead frame 4a, 4b are electrically connected to bonding pads 2a, 2b of each semiconductor chip 1a, 1b by gold wires 5a, 5b and the space including each semiconductor chip 1a, 1b and inner leads of lead frames 4a, 4b wire bonded thereto is molded by molding materials 6a, 6b so that only outer leads of lead frames 4a, 4b are exposed to both sides.
FIG. 2 is a cross sectional view showing a conventional stack package according to a second method. As shown in FIG. 2, two semiconductor chips 11a, 11b are arranged so that the formative sides of bonding pads 12a, 12b are opposite each other and lead frames 14a, 14b are adhered on bonding pad formative sides of each respective semiconductor chip 11a, 11b by adhesives 13a, 13b. Inner leads of each lead frame 14a, 14b are electrically connected to bonding pads 12a, 12b of each respective semiconductor 11a, 11b by gold wires 15a, 15b and the other side of lead the frame, that is not wire bonded to the bonding pad 12a of upper semiconductor chip 11a, is bonded to lead frame 14b of lower semiconductor chip 11b. The resulting structure is molded by molding material 16 so that only the outer lead of the lead frame of the lower semiconductor chip 11b is exposed to both sides.
However, the conventional stack packages have difficulty in installing heat sink, thereby lowering capacity of heat release. In addition, the conventional stack packages have several drawbacks as follows.
The stack package according to the first method has a structure in which two unit packages are stacked, thereby increasing the height. Furthermore, the electric signal paths of the upper package and that of the lower package are different relative to each other and therefore it is difficult to ensure electric reliability. Moreover, junction of upper and lower packages is accomplished by solder joint of each outer lead and therefore it is also difficult to ensure solder joint reliability.
In the stack package according to the second method, the distance between upper and lower gold wires for signal transmission is so close that signal noise may be generated when the two chips are operated. And, junction of lead frames is accomplished by laser welding, thereby increasing equipment investment. Moreover, it is impossible to rework the stack package.